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micro pmu with 1.2 a buck regulator and two 300 ma ldos data sheet adp5040 r ev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringemen ts of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered t rademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features input voltage range: 2. 3 v to 5.5 v one 1 .2 a b uck r egulator two 3 0 0 ma ldo s 20- l ead, 4 mm 4 mm lfcsp package over c urrent and t hermal protection soft s tart under voltage l ockout buck k ey s pecifications output v oltage r ange : 0.8 v to 3.8 v current m ode topology for excellent transient response 3 mhz operating frequency peak e fficiency up to 96% use s tiny multi layer inductors and capacitors mode pin selects f orced pwm or a uto pwm /psm modes 100% d uty c ycle low dropout mode ldo s k ey s pecifications out put v oltage r ange : 0.8 v to 5.2 v low v in from 1.7 v to 5.5 v stable with 2.2 f ceramic output capacitors high psrr l ow output noise low dropout voltage ? 40 c to + 125 c junction temperature range general description the adp5040 combines one high performance buck regulator and two low dropout regulators (ldo) in a small 20 - lead lfcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulator enables the use of tiny multilayer external components and minimizes board space . when the mode pin is set to logic high, the buck regulator operates in forced pulse width modulation ( pwm ) mode. when the mode pin is set to logic low, the buck regulator operates in pwm mo de when the load is around the nominal value. when the load current falls below a predefined threshold the regulator operates in power save mode (psm) improving the light - load efficiency. the low quiescent current, low dropout voltage, and wide input volta ge range of the adp5040 ldos extend the battery life of portable devices. the adp5040 ldos maintain a power supply rejection greater than 60 db for frequencies as h igh as 10 khz while operating with a low headroom voltage. each regulator in the adp5040 is activated by a high level on the respective enable pin. the output voltages of the regulators are programmed though e xternal resistor dividers to address a variety of applications. functional block dia gram sw c 3 1 f 09665-001 fb2 r4 r2 r1 r3 fb3 r3 r7 c2 2.2f c4 2.2f vout2 vout1 fb1 v in1 = 2.3v to 5.5v vin1 en1 vin2 en2 en3 vin3 v in3 = 1.7v to 5.5v en_ldo2 ldo2 (analog) buck pgnd mode vout3 ldo1 (digital) en_ldo1 avin avin r filt = 30? c5 4.7f v in2 = 1.7v to 5.5v v out1 at 1.2a v out2 at 300ma v out3 at 300ma c6 10f l1 1h c1 1f on off on off on off agnd en_bk psm/pwm fpwm figure 1 .
adp5040 data sheet rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 general specifications ................................................................. 3 buck specifications ....................................................................... 3 ldo1, ldo2 specifications ....................................................... 4 input and output capacitor, recommended specifications .. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 theory of operation ...................................................................... 25 power management unit ........................................................... 25 buck section ................................................................................ 26 ldo section ............................................................................... 27 applications information .............................................................. 29 buck external component selection ....................................... 29 ldo external component selection ...................................... 30 power dissipation/the rmal considerations ............................. 31 application diagram ................................................................. 33 pcb layout guidelines .................................................................. 34 suggested layout ........................................................................ 34 bill of materials ........................................................................... 35 factory programmable options ................................................... 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 12/ 11 revision 0: initial version
data sheet adp5040 rev. 0 | page 3 of 40 specifications general specificatio n s avin, v in1 = 2.3 v to 5.5 v; avin, v in1 vin2, vin3; vin2, vin3 = 1.7 v to 5.5 v, t j = ? 40 c to +125 c for minimum/maximum specifications, and t a = 25 c for typical specifications , unless otherwise noted. table 1 . parameter symbol descrip tion min typ max unit avin undervoltage lockout uvlo avin input voltage rising uvlo avinrise option 0 2.275 v option 1 3.9 v input voltage falling uvlo avinfall option 0 1.95 v option 1 3.1 v shutdown current i gnd - sd enx = gnd 0.1 2 a thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 20 c start - up time 1 buck t start1 250 s ldo1, ldo2 t start 2 v out2 , v out3 = 3.3 v 85 s e n x, mode, inputs input logic high v ih 2.5 v avin 5.5 v 1.2 v input logic low v il 2.5 v avin 5.5 v 0.4 v input leakage current v i- leakage e n x = a vin or gnd 0.05 1 a 1 start - up time is defined as the time from the moment en1 = en2 = en3 transfers from 0 v to v avin to the moment vout1, vout2, and vout3 r each e 90% of their nominal level. start - up times are shorter for individual channels if another channel is already enabled. see the typical performance characteristics section for more information. b uck specifications avin, vin1 = 2.3 v to 5.5 v; v out1 = 1.8 v ; l = 1 h; c in = 10 f ; c out = 10 f; t j = ?4 0c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 2. parameter symbol test conditions/comments min typ max unit input characteristics input voltage ran ge v in1 2.3 5.5 v output characteristics output voltage accuracy v out1 pwm mode, i load = 0 ma to 1200 ma ?3 +3 % line regulation (v out1 /v out1 )/v in1 pwm mode ? 0.05 %/v load regulation ( v out1 /v out1 )/ i out1 i load = ma to 1200 ma, pwm mode ? 0.1 %/a vo ltage feedback v fb1 0.485 0.5 0.515 v pwm to power save mode current threshold i psm_l 100 ma input current characteristics mode = ground dc operating current i noload i load = 0 ma, device not switching , all other channels disabled 21 35 a shutdown current i shtd en1 = 0 v, t a = t j = ?40c to +125c 0.2 1.0 a
adp5040 data sheet rev. 0 | page 4 of 40 parameter symbol test conditions/comments min typ max unit sw characteristics sw on resistance r pfet pfet, avin = vin1 = 3.6 v 180 240 m pfet, avin = vin1 = 5 v 140 190 m r nfet nfet, avin = vin1 = 3.6 v 170 235 m nfet, avin = vin1 = 5 v 150 210 m current limit i limit pfet switch peak current limit 1600 1950 2300 ma active pull-down en1 = 0 v 85 oscillator frequency f osc 2.5 3.0 3.5 mhz 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). ldo1, ldo2 specifications v in2 , v in3 = (v out2 ,v out3 + 0.5 v) or 1.7 v (whichever is greater) to 5.5v; avin, vin1 vin2, vin3; c in = 1 f , c out = 2.2 f; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3. parameter symbol conditions min typ max unit input voltage range v in2 , v in3 t j = ?40c to +125c 1.7 5.5 v operating supply current bias current per ldo 2 i vin2bias /i vin3bias i out3 = i out4 = 0 a 10 30 a i out2 = i out3 = 10 ma 60 100 a i out2 = i out3 = 300 ma 165 245 a total system input current i in includes all current into avin, vin1, vin2 and vin3 ldo1 or ldo2 only i out2 = i out3 = 0 a, all other channels disabled 53 a ldo1 and ldo2 only i out2 = i out3 = 0 a, buck disabled 74 a output voltage accuracy v out2 , v out3 100 a < i out2 < 300 ma, 100 a < i out3 < 300 ma v in2 = (v out2 + 0.5 v) to 5.5 v, v in3 = (v out3 + 0.5 v) to 5.5 v ?3 +3 % reference voltage v fb2 , v fb3 0.485 0.500 0.515 v regulation line regulation (v out2 /v out2 )/v in2 (v out3 /v out3 )/v in3 v in2 = (v out2 + 0.5 v) to 5.5 v v in3 = (v out3 + 0.5 v) to 5.5 v ?0.03 +0.03 %/ v i out2 = i out3 = 1 ma load regulation 3 (v out2 /v out2 )/i out2 (v out3 /v out3 )/i out3 i out2 = i out3 = 1 ma to 300 ma 0.002 0.0075 %/ma dropout voltage 4 v dropout v out2 = v out3 = 5.0 v, i out2 = i out3 = 300 ma 72 mv v out2 = v out3 = 3.3 v, i out2 = i out3 = 300 ma 86 140 mv v out2 = v out3 = 2.5 v, i out2 = i out3 = 300 ma 107 mv v out2 = v out3 = 1.8 v, i out2 = i out3 = 300 ma 180 mv active pull-down r pdldo en2/en3 = 0 v 600 current-limit threshold 5 i limit t j = ?40c to +125c 335 470 ma output noise out ldo2noise 10 hz to 100 khz, v in3 = 5 v, v out3 = 3.3 v 123 v rms 10 hz to 100 khz, v in3 = 5 v, v out3 = 2.8 v 110 v rms 10 hz to 100 khz, v in3 = 5 v, v out3 = 1.5 v 59 v rms out ldo1noise 10 hz to 100 khz, v in2 = 5 v, v out2 = 3.3 v 140 v rms 10 hz to 100 khz, v in2 = 5 v, v out2 = 2.8 v 129 v rms 10 hz to 100 khz, v in2 = 5 v, v out2 = 1.5 v 66 v rms
data sheet adp5040 rev. 0 | page 5 of 40 par ameter symbol conditions min typ max unit power supply rejection ratio psrr 1 khz, v in2 , v in3 = 3.3 v, v out2 , v out3 = 2.8 v, i out = 100 ma 66 db 100 khz, v in2 , v in3 = 3.3 v, v out2 , v out3 = 2.8 v, i out = 100 ma 57 db 1 mhz, v in2 , v in3 = 3.3 v, v out2 , v out3 = 2.8 v, i out = 100 ma 60 db 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 thi s is the input current into v in2 and v in3 , which is not delivered to the output load. 3 based on an end - point calculation using 1 ma and 30 0 ma loads. 4 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only for output voltages above 1.7 v. 5 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for exampl e, the current limit for a 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output cap acitor, recommended specifications table 4. parameter sy mbol conditions min typ max unit in put capacitance (buck) 1 c min1 t j = ?40c to +125c 4.7 40 f output capacitance (buck) 2 c min 2 t j = ?40c to +125c 7 40 f input and output capacitance 3 (ldo1, ldo2) c min 34 t j = ?40c to +125c 0.70 f capacitor esr r esr t j = ?40c to +125c 0.001 1 1 the minimum in put capa citance should be greater than 4 . 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the mi nimum capacitance specification is met. x7r and x5r type capacitors are recommended, whereas y5v and z5u capacitors are not recommended for use with the buck. 2 the minimum output capa citance should be greater than 7 f over the full range of operating con ditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended, whereas y5v and z5u capacitors are not r ecommended for use with the buck . 3 the minimum input and output capacitance should be greater than 0. 7 0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended, whereas y5v and z5u capacitors are not recommended for use with ldos.
adp5040 data sheet rev. 0 | page 6 of 40 absolute maximum rat ings table 5. parameter rating avin to a gnd ?0.3 v to +6 v vin1 to avin ?0.3 v to + 0.3 v pgnd to agdn ?0.3 v to + 0.3 v vin2 , vin3, voutx, e n x, mode, fbx, sw to a gnd ?0.3 v to (avin + 0.3 v ) sw to pgnd ?0.3 v to (vin1 + 0.3 v) sto rage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j - std -020 esd human body model 3000 v esd charged device model 1500 v esd machine model 200 v stresses above those listed under ab solute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposu re to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 20- lead , 0.5 mm p itch l fcsp 38 4.2 c/w esd caution
data sheet adp5040 rev. 0 | page 7 of 40 pin configuration an d function descripti ons 14 1 3 12 1 3 4 vout2 15 fb2 vin2 fb1 1 1 vout1 fb3 vin3 2 vout3 en3 5 nc 7 vin1 6 a vin 8 sw 9 pgnd 10 en1 19 nc 20 nc 18 nc 17 mode 16 en2 adp5040 t op view (not to scale) notes 1. exposed pad must be connected to system ground plane. 09665-002 figure 2 . pin configuration view from t op of the die table 7. preliminary pin function descriptions pin no. mnemonic description 1 fb3 ldo2 feedback in put . 2 vout3 ldo2 output voltage . 3 vin3 ldo2 input supply (1.7 v to 5.5 v) . 4 en3 enable ldo2. en3 = high : turn on ldo2; en3 = low: t urn off ldo2. 6 avin housekeeping input supply (2.3 v to 5.5 v) . 7 vin1 b uck input supply (2.3 v to 5.5 v) . 8 sw b uc k switching node . 9 pgnd dedicated power ground for b uck r egulator . 10 en1 enable buck. en1 = high : t urn on b uck; en1 = low: t urn off buck . 11 vout1 b uck output sensing node . 12 fb1 buck feedback input . 13 vin2 ldo1 input supply (1.7 v to 5.5 v) . 14 vout2 ldo1 output voltage . 15 fb2 ldo1 feedback input . 16 en2 enable ldo1. en2 = high : t urn on ldo1; en2 = low: t urn off ldo1. 17 mode buck mode. mode = high: b uck regul ator operates in fixed pwm mode; mode = low: b uck regulator operates in power save m ode (psm) at light load and in constant pwm at higher load. 5, 18, 19, 20 nc not connected . 0 epad exposed pad. ( agnd = analog ground) . the e xposed pad must be connected to the system ground p lane .
adp5040 data sheet rev. 0 | page 8 of 40 typical performance characteristics vin1 = vin2 = vin 3 = avi n = 5.0 v, t a = 25c, unless otherwise noted. ch4 2.0v/div 1m? b w 500m ch2 2.0v/div 1m? b w 20.0m ch3 2.0v/div 1m? b w 500m a ch2 1.88v 200s/div 1.0ms/s 1.0s/pt 4 2 3 v out1 v out2 v out3 09665-003 figure 3 . 3 - channel start - up waveforms ch1 ch2 ch3 ch4 a ch1 1.08v 200s/div 5.0ms/s 200ns/pt 1 2 3 4 v out3 v out2 v out1 i in 2.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 20.0m 300ma/div 1m? b w 20.0m 2.0v/div 1m? b w 20.0m 09665-004 figure 4 . total inrush current, all channels started simultaneously 1.0 0 2.4 2.9 3.4 3.9 4.4 4.9 5.4 i in (ma) v in (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 09665-005 figure 5 . system quiescent current (sum of all the input currents) vs. input voltage v out1 = 1.8 v, v out2 = v out3 = 3.3 v, (uvlo = 3.3 v) ch1 ch2 ch3 ch4 a ch1 2.32v 50s/div 2.0ms/s 500ns/pt 1 2 3 4 sw v out1 en i in 4.0v/div 1m? b w 20.0m 3.0v/div 1m? b w 500m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500m 09665-006 figure 6 . buck startup, v out1 = 3.3 v, i out2 = 20 ma ch1 ch2 ch3 ch4 a ch1 1.12v 50s/div 2.0ms/s 500ns/pt 1 2 3 4 sw v out1 en i in 8.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 500.0m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500.0m 09665-007 figure 7 . buck startup, v out1 = 1.8 v, i out = 20 ma ch1 ch2 ch3 ch4 a ch1 640mv 50s/div 2.0ms/s 500ns/pt sw v out1 en i in 8.0v/div 1m? b w 20.0m 2.0v/div 1m? b w 500.0m 200ma/div 1m? b w 20.0m 5.0v/div 1m? b w 500.0m 1 2 3 4 09665-008 figure 8 . buck startup, v out1 = 1.2 v, i out = 20 ma
data sheet adp5040 rev. 0 | page 9 of 40 3.90 3.70 0.01 0.1 1 output voltage (v) output current (a) 3.72 3.74 3.76 3.78 3.80 3.82 3.84 3.86 3.88 ?40c +25c +85c 09665-009 figure 9 . buck load regulation across temperature, v out1 = 3.8 v, auto mode 3.39 3.37 3.35 3.33 3.31 3.29 3.25 3.27 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-010 figure 10 . buck load regulation across temperature, v out1 = 3.3 v, auto mode 1.820 1.815 1.810 1.800 1.805 1.795 1.790 1.780 1.785 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-0 1 1 figure 11 . buck load regulation across temperature, v out1 = 1.8 v, auto mode 1.24 1.23 1.22 1.21 1.20 1.19 1.18 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-012 figure 12 . buck load regulation across temper ature, v out1 = 1.2 v, auto mode 3.90 3.88 3.86 3.70 3.72 3.74 3.76 3.78 3.80 3.82 3.84 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-013 figure 13 . buck load regulation across temperature, v out1 = 3.8 v, pwm mode 3.32 3.31 3.30 3.25 3.26 3.27 3.28 3.29 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-014 figure 14 . buck load regulation across temperature, v out1 = 3.3 v, pwm mode
adp5040 data sheet rev. 0 | page 10 of 40 1.820 1.815 1.810 1.800 1.805 1.795 1.790 1.780 1.785 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-015 figure 15 . buck load regulation across temperature, v out1 = 1.8 v, pwm mode 1.205 1.200 1.195 1.185 1.190 1.180 0.01 0.1 1 output voltage (v) output current (a) ?40c +25c +85c 09665-016 figure 16 . buck load regulation across temperature, v out1 = 1.2 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v 09665-017 figure 17 . buck efficiency vs. load current, across input voltage, v out1 = 3.8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v 09665-018 figure 18 . buck efficiency vs. load current, across input voltage, v out1 = 3.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5v v in = 4.5v v in = 3.6v 09665-019 figure 19 . buck efficiency vs. load cur rent, across input voltage, v out1 = 3.3 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 5.5 v in = 3.6 v in = 4.5 09665-020 figure 20 . buck efficiency vs. load current, across input voltage, v out1 = 3.3 v, pwm mode
data sheet adp5040 rev. 0 | page 11 of 40 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09665-021 figure 21 . buck efficiency vs. load current, across i nput voltage, v out1 = 1.8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09665-022 figure 22 . buck efficiency vs. load current, across input voltage, v out1 = 1.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09665-023 figure 23 . buck efficiency vs. load current, across input voltage, v out1 = 1.2 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09665-024 figure 24 . buck efficiency vs. load current, across input voltage, v out1 = 1.2 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-025 figure 25 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 3.3 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-026 figure 26 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 3.3 v, pwm mode
adp5040 data sheet rev. 0 | page 12 of 40 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-027 figure 27 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.8 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-028 figure 28 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.8 v, pwm mode 100 0 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-029 figure 29 . buck efficiency vs. load current, across temperat ure, v in = 5.0 v, v out1 = 1.2 v, auto mode 100 0 0.001 0.01 0.1 1 efficiency (%) output current (a) 10 20 30 40 50 60 70 80 90 ?40c +25c +85c 09665-030 figure 30 . buck efficiency vs. load current, across temperature, v in = 5.0 v, v out1 = 1.2 v, pwm mode 2.5 2.0 0.5 1.0 1.5 0 3.4 3.9 4.4 4.9 5.4 output current (a) v in (v) v out = 3.3v 09665-031 figure 31 . buck dc current capability vs. input vol tage 2.0 1.8 0.2 0.4 0.6 0.8 1.6 1.4 1.2 1.0 0 2.4 3.9 3.4 2.9 4.4 4.9 5.4 output current (a) v in (v) v out = 1.8v 09665-032 figure 32 . buck dc current capability vs. input voltage
data sheet adp5040 rev. 0 | page 13 of 40 2.0 1.8 0.2 0.4 0.6 0.8 1.6 1.4 1.2 1.0 0 2.4 3.9 3.4 2.9 4.4 4.9 5.4 output current (a) v in (v) v out = 1.2v 09665-033 figure 33 . buck dc current capability vs. input voltage 2.80 2.82 2.84 2.86 2.88 2.90 2.92 2.94 0 1.2 1.0 0.2 0.4 0.6 0.8 frequency (mhz) output current (a) ?40c +25c +85c 09665-034 figure 34 . buck switching frequency vs. output curr ent, across temperature, v out1 = 1.8 v, pwm mode ch2 ch3 ch4 a ch1 640mv 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09665-035 figure 35 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch1 640mv 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09665-036 figure 36 . typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch3 1.14v 5s/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09665-037 figu re 37 . typical waveforms, v out1 = 1.2 v, i out1 = 30 ma, auto mode ch2 ch3 ch4 a ch1 640mv 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 10.0mv/div 20.0m 2 3 4 09665-038 figure 38 . typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode
adp5040 data sheet rev. 0 | page 14 of 40 ch2 ch3 ch4 a ch1 640mv 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 20.0mv/div 20.0m 2 3 4 09665-039 figure 39 . typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, pwm mode ch2 ch3 ch4 a ch3 1.14v 200ns/div 500ms/s 2.0ns/pt sw v out i sw 200ma/div 1m? b w 20.0m 3.0v/div 1m? b w 20.0m 40.0mv/div 20.0m 2 3 4 09665-040 figure 40 . typical waveforms, v out1 = 1.2 v, i out1 = 30 ma, pwm mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-041 figure 41 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, i o ut1 = 5 ma, auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 30.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-042 figure 42 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.8 v, i out1 = 5 ma, auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-043 figure 43 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.2 v, i out1 = 5 ma, auto mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-044 figure 44 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode
data sheet adp5040 rev. 0 | page 15 of 40 ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 20.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 400m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-045 figure 45 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.8 v, pwm mode ch1 ch2 ch3 a ch3 4.48v sw v out v in 3.0v/div 50.0mv/div 1m? b w 20.0m 1.0v/div 2 1 3 b w 20.0m b w 20.0m 200s/div 1.0ms/s 1.0s/pt 09665-046 figure 46 . buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-047 figure 47 . buck respon se to load transient, i out1 = 20 ma to 200 ma, v out1 = 3.3 v, auto mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-048 figure 48 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 3.3 v, auto mode ch1 ch2 ch3 a ch3 150m a v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 2 1 3 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-049 figure 49 . buck response to lo ad transient, i out1 = 20 ma to 200 ma, v out1 = 1.8 v, auto mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-050 figure 50 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.8 v, auto mode
adp5040 data sheet rev. 0 | page 16 of 40 ch1 ch2 ch3 a ch3 94.0m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 120m 1m? b w 20.0m 100ma/div 1 b w 20.0m 200s/div 500ks/s 2.0s/pt i out 09665-051 figure 51 . buck response to load trans ient, i out1 = 20 ma to 200 ma, v out1 = 1.2 v, auto mode ch1 ch2 ch3 a ch3 92.0m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 120m b w 20.0m 200ma/div 1 b w 20.0m 200s/div 500ks/s 2.0s/pt i out 09665-052 figure 52 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.2 v, auto mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-053 figure 53 . buck response to load transient, i o ut1 = 20 ma to 200 ma, v out1 = 3.3 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-054 figure 54 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 3.3 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 50.0mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-055 figure 55 . buck response to load transient, i out1 = 20 m a to 200 ma, v out1 = 1.8 v, pwm mode ch1 ch2 ch3 a ch3 150m a 2 3 v out sw 4.0v/div 100mv/div 1m? b w 20.0m 1m? b w 20.0m 300ma/div 1 b w 20.0m 500s/div 20.0ms/s 50.0ns/pt i out 09665-056 figure 56 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.8 v, pwm mode
data sheet adp5040 rev. 0 | page 17 of 40 sw ch1 ch2 ch3 a ch3 94.0m a 2 3 v out 4.0v/div 50.0mv/div 1m? b w 120.0m b w 20.0m 100ma/div 1 b w 20.0m 200s/div 500ks/s 2.0ns/pt i out 09665-057 figure 57 . buck response to load transient, i out1 = 20 ma to 200 ma, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch3 92.0m a 2 3 v out 4.0v/div 50.0mv/div 1m? b w 20.0m 20.0m 200ma/div 1 20.0m 200s/div 500ks/s 2.0ns/pt sw i out 09665-058 figure 58 . buck response to load transient, i out1 = 50 ma to 500 ma, v out1 = 1.2 v, pwm mode ch1 ch2 ch3 a ch1 1.72v 2 3 v out 2.0v/div 2.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09665-059 figure 59 . ldo1, ldo2 startup, v out = 4.7 v, i out = 5 ma ch1 ch2 ch3 a ch1 1.72v v out 2.0v/div 2.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09665-060 figure 60 . ldo1, ldo2 startup, v out = 3.3 v, i out = 5 ma ch1 ch2 ch3 a ch1 760mv 2 3 v out 2.0v/div 1.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09665-061 figure 61 . ldo1, ldo2 startup, v out = 1.8 v, i out = 5 ma ch1 ch2 ch3 a ch1 1.72v 2 3 v out 2.0v/div 1.0v/div b w 20.0m 1m? b w 20.0m 200ma/div 1 1m? b w 20.0m 50.0s/div 200ms/s 5.0ns/pt i in en 09665-062 figure 62 . ldo1, ldo2 startup, v out = 1.2 v, i out = 5 ma
adp5040 data sheet rev. 0 | page 18 of 40 4.758 4.708 4.658 4.608 0.001 0.01 0.1 output voltage (v) output current (a) 5.5v 5.0v 09665-063 figure 63 . ldo1, ldo2 load regulation across input voltage, v out = 4.7 v 3.40 3.20 0.001 0.01 0.1 output voltage (v) output current (a) 5.5v 3.6v 4.5v 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 09665-064 figure 64 . ldo1, ldo2 load regulation across input voltage, v out = 3.3 v 1.800 1.770 0.001 0.01 0.1 output voltage (v) output current (a) 1.775 1.780 1.785 1.790 1.795 3.6v 4.5v 5.5v 2.8v 09665-065 figure 65 . ldo1, ldo2 load regulation a cross input voltage, v out = 1.8 v 1.220 1.180 0.001 0.01 0.1 output voltage (v) output current (a) 3.6v 4.5v 5.5v 2.8v 1.185 1.190 1.195 1.200 1.205 1.210 1.215 09665-066 figure 66 . ldo1, ldo2 load regulation across input voltage, v out = 1.2 v 3.40 3.20 0.001 0.01 0.1 output voltage (v) output current (a) 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 ?40c +25c +85c 09665-067 figure 67 . ldo1, ldo2 load regulation across temperature, v in = 3.6 v, v out = 3.3 v 1.800 1.770 0.001 0.01 0.1 output voltage (v) output current (a) ?40c +25c +85c 1.775 1.780 1.785 1.790 1.795 09665-068 fig ure 68 . ldo1, ldo2 load regulation across temperature, v in = 3.6 v, v out = 1.8 v
data sheet adp5040 rev. 0 | page 19 of 40 1.220 1.180 0.001 0.01 0.1 output voltage (v) output current (a) 1.185 1.190 1.195 1.200 1.205 1.210 1.215 ?40c +25c +85c 09665-069 figure 69 . ldo1, ldo2 load regulation across temperature, v in = 3.6 v, v out = 1.2 v 4.75 4.73 4.65 4.67 4.69 4.71 5.0 5.1 5.5 5.4 5.3 5.2 output voltage (v) input voltage (v) 100a 1ma 10ma 100ma 200ma 09665-070 figure 70 . ldo1, ldo2 line regulation across input voltage, v out = 4.7 v 3.310 3.280 3.6 3.9 4.2 4.5 5.1 4.8 5.4 output voltage (v) input voltage (v) 3.285 3.290 3.295 3.300 3.305 100a 1ma 10ma 100ma 200ma 09665-071 figure 71 . ldo1, ldo2 line regulation across input voltage, v out = 3.3 v 1.820 1.790 2.5 3.0 3.5 4.0 5.0 4.5 5.5 output voltage (v) input voltage (v) 100a 1ma 10ma 100ma 200ma 1.795 1.800 1.805 1.810 1.815 09665-072 figure 72 . ldo1, ldo2 line regulation across input voltage, v out = 1.8 v 1.201 1.192 2.5 5.5 output voltage (v) input voltage (v) 1.193 1.194 1.195 1.196 1.197 1.198 1.199 1.200 3.0 3.5 4.0 4.5 5.0 100 a 1m a 10m a 100m a 200m a 09665-073 figure 73 . ldo1, ldo2 line regulation across input voltage, v out = 1.2 v 200 0 0 0.05 0.10 0.15 0.20 0.25 0.30 ground current (a) output current (a) 20 40 60 80 100 120 140 160 180 09665-074 figure 74 . ldo1, ldo2 ground current vs. output current, v out = 3.3 v
adp5040 data sheet rev. 0 | page 20 of 40 200 0 3.8 4.3 4.8 5.3 ground current (a) input voltage (v) 20 40 60 80 100 120 140 160 180 0.000001a 0.0001a 0.001a 0.01a 0.1a 0.15a 0.3a 09665-075 figure 75 . l do1, ldo2 ground current vs. input voltage, across output load (a), v out = 3.3 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09665-076 figure 76 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 4.7 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09665-077 figure 77 . ldo1, ldo2 respon se to load transient, i out from 10 ma to 200 ma, v out = 4.7 v ch2 ch3 a ch3 42.0m a 2 v out 30.0mv/div 50.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09665-078 figure 78 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 3.3 v ch2 ch3 a ch3 89.6m a 2 v out 50.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09665-079 figure 79 . ldo1, ldo2 response to load transie nt, i out from 10 ma to 200 ma, v out = 3.3 v ch2 ch3 a ch3 89.6m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09665-080 figure 80 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 1.8 v
data sheet adp5040 rev. 0 | page 21 of 40 ch2 ch3 a ch3 89.6m a 2 v out 50.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 120m 200s/div 500ks/s 2.0s/pt i out 09665-081 figure 81 . ldo1, ldo2 response to load transient, i out from 10 m a to 200 ma, v out = 1.8 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09665-082 figure 82 . ldo1, ldo2 response to load transient, i out from 1 ma to 80 ma, v out = 1.2 v ch2 ch3 a ch3 27.2m a 2 v out 30.0mv/div 80.0ma/div b w 20.0m 3 1m? b w 20.0m 200s/div 5.0ms/s 200ns/pt i out 09665-083 figure 83 . ldo1, ldo2 response to load transient, i out from 10 ma to 200 ma, v out = 1.2 v ch2 ch3 a ch3 4.84v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09665-084 figure 84 . ldo1, ldo2 response to line transient, input voltage from 4.5 v to 5.5 v, v out = 3.3 v ch2 ch3 a ch3 4.86v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 500s/div 1.0ms/s 1.0s/pt v in 09665-085 figure 85 . ldo1, ldo2 response to line transient, input voltage from 4.5 v to 5.5 v, v out = 1.8 v ch2 ch3 a ch3 4.48v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09665-086 figure 86 . ldo1, ldo2 response to line transient, input voltage from 4.5 v to 5.5 v, v out = 1.2 v
adp5040 data sheet rev. 0 | page 22 of 40 ch2 ch3 a ch3 4.02v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09665-087 figure 87 . ldo1, ldo2 response to line transient, input voltage from 3.3 v to 3.8 v, v out = 1.8 v ch2 ch3 a ch3 4.84v 2 v out 20.0mv/div 1.0v/div b w 20.0m 3 1m? b w 20.0m 200s/div 1.0ms/s 1.0s/pt v in 09665-088 figure 88 . ldo1, ldo2 response to line transient, input voltage from 3.3 v to 3.8 v, v out = 1.2 v 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3.6 4.1 4.6 5.1 5.6 output current (a) v in (v) v out = 3.3v 09665-089 figure 89 . ldo1, ldo2 output current capability vs. input voltage load (ma) rms noise ( v) 100 10 0.0001 0.001 0.01 0.1 1 10 100 1k ch2; v out = 3.3v; v in = 5v ch2; v out = 3.3v; v in = 3.6v ch2; v out = 2.8v; v in = 3.1v ch2; v out = 1.5v; v in = 5v ch2; v out = 1.5v; v in = 1.8v 09665-104 figure 90 . ldo1 output noise vs. load current, across input and output voltage load (ma) rms noise ( v) 100 10 ch3; v out = 3.3 v ; v in = 5v ch3; v out = 3.3 v ; v in = 3.6v ch3; v out = 2.8 v ; v in = 3.1v ch3; v out = 1.5 v ; v in = 5v ch3; v out = 1.5 v ; v in = 1.8v 0.0001 0.001 0.01 0.1 1 10 100 1k 09665-105 figure 91 . ldo2 output noise vs. load current, across input and output voltage 10 100 1k 10k 100k 1m 10m frequenc y (hz) noise ( v/ hz) 100 10 1.0 0.1 0.01 v out2 = 3.3 v , v in2 = 3.6 v , i load = 300m a v out2 = 1.5 v , v in2 = 1.8 v , i load = 300m a v out2 = 2.8 v , v in2 = 3.1 v , i load = 300m a 09665-106 figure 92 . ldo1 noise spectrum ac ross output voltage, v in = v out + 0.3 v
data sheet adp5040 rev. 0 | page 23 of 40 noise (v/hz) 100 10 1 0.1 0.01 1 10 100 1k frequenc y (hz) 10k 100k 1m v out3 = 3.3 v , v in3 = 3.6 v , i load = 300m a v out3 = 1.5 v , v in3 = 1.8 v , i load = 300m a v out3 = 2.8 v , v in3 = 3.1 v , i load = 300m a 09665- 1 15 figure 93 . ldo2 noise spectrum across output voltage, v in = v out + 0.3 v 100 10 1.0 0.1 0.01 10 100 1k 10k 100k 1m 10m frequenc y (hz) noise ( v/ hz ) v out2 = 3.3v, v in2 = 3.6v, i load = 300ma v out3 = 3.3v, v in3 = 3.6v, i load = 300ma v out2 = 1.5v, v in2 = 1.8v, i load = 300ma v out3 = 1.5 v , v in3 = 1.8 v , i load = 300m a v out2 = 2.8 v , v in2 = 3.1 v , i load = 300m a v out3 = 2.8 v , v in3 = 3.1 v , i load = 300m a 09665-108 figure 94 . ldo1 vs. ldo2 noise spectrum ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09665-109 figure 95 . ldo 2 psrr across output load, v in3 = 3.3 v, v out3 = 2.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09665- 1 10 figure 96 . ldo2 psrr across output load, v in3 = 3.1 v, v out3 = 2.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 09665- 11 1 figure 97 . ldo2 psrr across output load, v in3 = 5.0 v, v out3 = 3.3 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09665- 1 12 figure 98 . ldo2 psrr across output load, v in3 = 3.6 v, v out3 = 3.3 v
adp5040 data sheet rev. 0 | page 24 of 40 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09665- 1 13 figure 99 . ldo1 psrr across output load, v in2 = 5.0 v, v out2 = 1.5 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequenc y (hz) psrr (db) 1m a 10m a 100m a 200m a 300m a 09665- 1 14 figure 100 . ldo1 psrr across ou tput load, v in2 = 1.8 v, v out2 = 1.5 v
data sheet adp5040 rev. 0 | page 25 of 40 theory of operation pw m/ psm c o n t r o l buck 1 dr i ver an d an t i sh oo t t hr o u g h psm c o mp adp5040 vo u t 1 fb1 vi n 1 avin sw pg n d ag n d vi n 2 fb2 vo u t 2 vi n 3 en l d o 1 60 0 ? enb k en l d o 2 60 0 ? vo u t 3 fb3 09665-090 oscillator thermal shutdown vd da pwm comp gm error amp 85? soft start system undervoltage lock out ldo1 control ldo2 control vdda enable & mode control enldo1 enbk enldo2 mode sel mode en1 en2 en3 opmode_fuses vdda i limit low current figure 101 . functional block diagram power management uni t the adp5040 is a micro power management unit (micro pmu ) combing one step - down (buck) dc - to - dc regulator and two low dropout linear regulator s (ldo s ). the high switching frequency and tiny 20 - pin lfcsp package allow for a small power management solution. the regulators are act ivated by a logic level high appl ied to the respective en pin . the en1 pin controls the b uck regulator, the en2 pin controls ldo1 , and the en3 pin controls ldo2. t he mode pin control s the b uck switching operation . the r egulator output voltages are set through external resistor dividers. w hen a regulator is turned on, the output voltage ramp is controlled th r ough a soft start circuit to avoid a large inrush current due to the discharged output capacitors. the buck regulator can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the switching frequency of the buck is always constant and does not change with the load current. if the mode pin is at a logic low level, the switching regulator operate s in auto pwm/psm mod e. in this mode, the regulator opera te s at fixed pwm frequency w hen the load current is above the power saving current thresh old. when the load curr ent falls below the power save current threshold, the regulator enters power saving mode , where the switching occurs in bursts. the burst repeti tion rate is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses.
adp5040 data sheet rev. 0 | page 26 of 40 thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown cir cuit turns off the b uck and the ldo s. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient tempe rature. a 20c hysteresis is included in the thermal shutdown circuit so that when thermal shut down occurs, the buck and the ldo s do not return to normal operation until the on - chip temperature drops below 130c. when coming out of thermal shutdown, a ll regulators start with soft start control . undervoltage lockout to protect against battery dischar ge, undervoltage lockout (uvlo) circu itry is integrated in the adp5040 . if the input voltage on a vin drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channel, both the power swi tch and the synchronous rectifier turn off. when the voltage on a vin rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for 5 v applications. for these models, the device reaches the turn - off threshold when the input supply drops to 3.65 v typical. enable/shutdown the adp5040 ha s individual control pin s for each regulator. a logic level high applied to the e n x pin activate s a regulator, whereas a logic level low turns off a regulator. active pull - down the adp5040 can be purchased with the active pull - down option enabled. the pull - down resistors are connected be tween each regulator output and agnd. the pull - downs are enabled, when the regulators are turned off. the typical value of the pull - down resis tor is 600 for the ldos and 8 5 for the buck. buck section the buck use s a fixed frequency and high speed current mode architecture. the buck operate s with an input voltage of 2. 3 v to 5.5 v. the b uck output voltage is set though external resistor div ider s, as shown in figure 102 . vout1 must be connected to the output capacitor. vfb1 is internally set to 0.5 v. the output voltage can be set from 0.8 v to 3.8 v. buck vout1 vout1 sw vin1 fb1 agnd c5 10f r1 r2 l1 ? 1h 09665-091 figure 102 . buck external output volt age setting control scheme the buck operate s with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency , but operation shifts to a power save mode (psm) control scheme at light loads to lower the regulation po wer losses. when operating in fixed frequency pwm mode, the duty cycl e of the integrated switches is adjusted and regulate s the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner , with higher outpu t voltage ripple. dur ing part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the buck operate s at a fixed frequency of 3 mh z , set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and tu rns on the nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak in ductor current threshold. power save mode (psm) the buck smoothly transition s to psm operation when the load current decreases below the psm current threshold. when the buck enter s p ower save mode, an offset is in troduced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level that is approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacit or discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold.
data sheet adp5040 rev. 0 | page 27 of 40 the adp5040 has a dedicated mode pin controlling the psm and pwm operation. a high logic level applied to the mode pin forces the buck to operate in pwm mode. a l ogic level low sets the buck to op erate in auto psm/pwm. psm current threshold the psm current threshold is set to 100 ma. the buck employ s a scheme that enables this current to remain accurately con - trolled, independent of input and output voltage levels. this scheme also ensures that the re is very little hysteresis between the psm current threshold for entry to , and exit from , the psm mode . the psm current thre shold is optimized for excellent efficiency over all load currents. short - circuit protection the buck include s frequ ency foldback to prevent current runaway on a hard short at the output . when the voltage at the feedback pin falls belo w half the internal reference voltage , indicating the possi bility of a hard short at the output, the switching frequency is reduced to half the interna l oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the buck ha s an internal soft start function that ramps the output voltage in a controlled m anner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit the buck has protection circuitry to limit the amo unt of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. th e negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a dropp in g input voltage or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the b uck immediately restarts pwm regulation without allowing overshoot on the output voltage. ldo section the adp5040 contains two ldos with low quiescent curre nt that provide output currents up to 300 ma. the low 1 0 a typical quiescent current at no load makes the ldo ideal for battery - operated portable equipment. the ldo s operate with an input voltage range of 1.7 v to 5.5 v. the wide operating range makes these ldos suita ble for cascade configuration s where the ld o supply voltage is provided from the buck regulator. each ldo output voltage is set though external resistor divider s as shown in figure 103 . v fb2 an d v fb3 are internally set to 0.5 v . the output voltage can be s e t from 0.8 v to 5.2 v. ld01, ld02 r a r b vin2, vin3 vout2, vout3 vout2, vout3 fb2, fb3 c7 2.2f 09665-092 figure 103 . ldos external output voltage setting t he ldos also provide high power supply rejection ratio (psrr) , low output noise, and excellent line and load transient response with small 1 f ceramic inpu t and output capacitor s. ldo2 is optimized to supply analog circuits because it offers better noise performance compared to ldo1. ldo1 should be used in applications where noise performance is not critical.
adp5040 data sheet rev. 0 | page 28 of 40 po r st andb y a vi n < vu vl o a ll en x = l o w all regulators activated a vi n < vu vl o i n t erna l c i rcu i t b i a sed r eg u l a t o r s n o t ac t i va t ed no power applied to avin. all regulators turned off transition state 09665-096 end o f po r a vi n > vu vl o en x = h ig h no power active figure 104 . adp5040 state flow
data sheet adp5040 rev. 0 | page 29 of 40 a pplications information buck external compon ent selection trade - offs between performance parameters such as efficiency and transient response are made by varying the choice of external compo nents in the applications circuit , as shown in figure 1 . feedback resistors referring to figure 102, the total combined resistance for r1 and r2 is not to exceed 400 k . inductor the high switching frequency of the adp5040 buck allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 .0 h. suggested inductors are shown in table 8 . the peak - to - peak inductor current ripple is calculated using the following equation: l f v v v v i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the in ductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 ) ( ripple max load peak i i i + = table 8 . suggest ed 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 3.2 2.5 1.5 2300 54 tayo yuden cbc322st1r0mr 3.2 2.5 2.5 2000 71 coilcraft xfl4020 - 102me 4.0 4.0 2.1 5400 11 coilcraft xpl2010 - 102ml 1.9 2.0 1.0 1800 8 9 toko mdt2520 - cn 2.5 2.0 1.2 1350 85 inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losse s are related to the magnetic permeability of the core mate rial. because the buck is high switching frequency dc - to - dc conv erter , shielded ferrite core material is recomme nded for its low core losses and low emi. output capacitor higher output capacitor values reduce the output voltage ripple and improve load transien t response. when choosing the capacitor value, it is also important to account for the loss of capacitance d ue to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec - trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the ne cessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are highly recom mended for best performance. y5v an d z5u dielectrics are not recommended for use with any dc - to - dc converter because of their po or temperature and dc bias characteristics. the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu - lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (temp co) over ?40c to +85c is assumed to be 15% for an x5r dielec tric. the tolerance of the capacitor (tol) is assumed to be 10% , and c out is 9.2481 f at 1.8 v, as shown in fig ure 105 . substituting these values in the e quation yields c eff = 9.24 f (1 ? 0.15) (1 ? 0.1) = 7.07 f to guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 1 0 1 2 0 1 2 3 4 5 6 dc b i a s vo lta g e (v) capacitance (f) 09665-097 fig ure 105 . typical capacitor performance the peak - to - peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: ( ) out sw in out sw ripple ripple c l f v c f i v = 2 2 8
adp5040 dat a sheet rev. 0 | page 30 of 40 capacitors with lower equivalen t series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. table 9 . suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk107bj106ma - t 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 the buck regulator require s 10 f output capacitors to guaran - t ee stability and response to rapid load variations and to transition in and out the pwm/psm modes. in certain applications, wher e the buck regulator powers a processor, the operating state is known because it is controlled by software. in this condition, t he processor can drive the mode pin according to the ope rating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regula tor does not expect a large load var iation when working in psm mode ( see figure 106 ) . sw vi n 1 vi n 2 vi n 3 vo u t 1 vo u t 2 pg n d vo u t 3 c 1 10 f c 2 1 f c 3 1 f pr o c ess o r vc o r e vdd i o mo d e g pio 1 en x g pio [x :y ] 3 r5 fb3 r6 r1 r2 r3 r4 vanalog fb1 fb2 c5 2.2f c4 4.7f c6 2.2f 09665-098 ad p 504 0 mi cr o pmu v in 2.3v to 5.5v r flt 30? l1 1h avin analog subsystem figure 106 . processor system power management with psm/pwm control input capacitor a h igher value in put capacitor help s to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v v v v i i ) ( ) ( ? to minimize supply noise, place the input capacitor as close to the vin pin of the buck as possible. as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 f and a maximum of 10 f. a list of sugge sted capacitors is shown in table 10. table 10 . suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me19d 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 panasonic x5r ecj - 0eb0j475m 0402 6.3 ldo e xternal c omponent s election feedback resistors referring to figure 103 the maximum value of rb is not to exceed 200 k . output capacitor the adp5040 ldo s are designed for operation with small, space - saving ceramic capacitors, but they funct ion with most commonly used capacitors as long as care is taken with the esr value. the esr of the out put capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recom mended to ensure stability of the ldo . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ldo to large changes in load current. when operating at output currents highe r than 200 ma a minimum of 2.2 f capacitance with an esr of 1 ? or less is recom mended to ensure stability of the ldo . table 11. suggested 2.2 f capacitors vendor type model case size voltage rating (v) murata x5r GRM188B31A225K 0402 10.0 tdk x5r c1608jb0j225kt 0402 6.3 panaso nic x5r ecj1vb0j225 k 0402 6.3 taiyo yuden x5r jmk107bj225kk - t 0402 6.3 input bypass capacitor connecting 1 f capacitor s from vin2 and vin3 to ground reduce s the cir cuit sensitivity to printed circuit board (pcb) layout, especially when long input t race s or high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it.
data sheet adp5040 rev. 0 | page 31 of 40 table 12. suggested 1.0 f capacitors vendor type model case size voltage rating (v) murata x5r grm155r61a105me15 0402 10.0 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv - f 0402 10.0 input and output capacitor properties use any good quality ceramic capacitor with the adp5040 as long as it meet s the minimum capacitance and maximum esr r equirements. ceramic capacitors are manufactured with a vari ety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tempe - rature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 107 depicts the capacitanc e vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general, a capacitor in a larger package or higher voltag e rating exhibits bette r stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera - ture range and is not a function of package or voltage rating. 1 . 2 1 . 0 0 . 8 0 . 6 0 . 4 0 . 2 0 0 1 2 3 4 5 6 dc b i a s vo lta g e (v) capacitance (f) 09665-099 figure 107 . capacitance vs. voltage characteristic use the following equation to determine the worst - case capa - citance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. t empco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capa citor (tol) is assumed to be 10% , and c bias is 0.94 f at 1.8 v as shown in figure 107. substituting these val ues into the following equation yields: c eff = 0.94 f (1 C 0.15) (1 C 0.1) = 0.72 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the pe rformance of the adp5040 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application. power dissipation/thermal considerations the adp5040 is a highly efficient micropo wer management unit (micro pmu), and in most cases the power dissipated in the device is not a concern. however, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowab le operating limit (125c). when the junction temperature exceeds 150c, the adp5040 turns off all the regulators , allowing the device to cool down. once the die temperature falls below 135c, the adp5040 resumes normal operation. this section provides guidelines to calculate the power dissi - pated in the device and to make sure the adp5040 operates below the maximum al lowable junction temperature. the efficiency for each regulator on the adp5040 is given by 100% = ( 1 ) where: is effi ciency . p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1 ? )/ ( 2b ) power dissipation can be calculated in several ways. the most intuitive and practical way is to measure the power dissipated at the input and all the outputs. the measurements should be performed at the worst - case conditions (voltages, currents, and temperature). the difference between input and output power is dissipated in the device and the inductor. use e quation 4 to derive the power lost in the inductor, and from this use equation 3 to calculate the power dissipation in the adp5040 buck regulator. a second method to estimate the power dissipation uses the eff iciency curves provided for the buck regulator, whereas the power lost on a ldo is calculated using equation 12. when the buck efficiency is known, use equation 2b to derive the total power lost in the buck regula tor and inductor. u se equation 4
adp5040 dat a sheet rev. 0 | page 32 of 40 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the ldos to find the total dissipated power. note that the buck efficiency curves are typical valu es and may not be provided for all possible combinations of v in , v out , and i out . to account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. a third way to estimate the power dissipation i s analytical and involves modeling the losses in the buck circuit provided by equation 8 to equation 11 and the losses in the ldos provided by equation 12. buck regulator power dissipation the power loss of the buck regulator is approximated by p loss = p d buck + p l ( 3 ) where: p d buck is the power dissipation on the adp5040 buck regulator . p l is the inductor power losses. the inductor losses are external to the device and they d o not have any effect on the die t emperature. the inductor losses are estimated (without core losses) by l rms out1 l dcr i p ? 2 ) ( ( 4 ) w here: dcr l is the inductor series resistance. i out 1(rms) is the rms load current of the buck regulator . /12 + 1 ) ( r i i out1 rms out1 = ( 5) where r is the normali zed inductor ripple current . r v out1 (1 ? d )/( i out1 l f sw ) (6) where: l is inductance . f sw is switching frequency . d is duty cycle. d = v out1 / v in1 (7) the adp5040 buck regulator power dissipation, p d bu ck , includes the power switch conductive losses, the switch losses, and the transition losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the applicatio n is . equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran ( 8 ) the power switch conductive losses are due to the output current, i out 1 , flowing through the pmosfet and the nmos f et powe r switches that have internal resistance, r dson - p and r dson - n . the amount of conductive power loss is found by : p cond = [ r dson - p d + r dson - n (1 C d )] i out 1 2 (9 ) for the adp5040 , at 125c junction tempera ture and v in1 = 3.6 v, r dson - p is approximately 0.2 , and r dson - n is approximately 0.16 . at v in1 = 2.3 v, these values change to 0.31 and 0.21 , respectively, and at v in1 = 5.5 v, the values are 0.16 and 0.14 , respectively. switching losses are associated with the current dr awn by the driver t o turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by : p sw = (c gate - p + c gate - n ) v in1 2 f sw ( 10) where: c gate - p is the pmosfet gate capacitance. c gate - n is the nmosfet gate capacitance. for the adp5040 , the total of ( c gate - p + c g ate - n ) is approximately 150 pf. the t ransition losses occur because the pmosfet cannot be turned on or off instantaneously , and the sw node takes some t ime to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by : p tran = v in1 i out1 (t rise + t fall ) f sw (11) where t rise and t fall are the rise time and the fall time of the switching node, sw. fo r the adp5040 , the rise and fall time s of sw are in the order of 5 ns. if the preceding equations and parameters are used for estimati ng the converter efficiency, note that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter performance also depends on the choice of passive component s and board layout; therefore, a sufficient safety margin should be included in the estimate. ldo regulator power dissipation the power loss of a ldo regulator is given by : p dldo = [( v in C v out ) i load ] + ( v in i gnd ) (12) where: i load is the load current of the ldo regulator . v in and v out are input and output voltages of the ldo , respectively. i gnd is the grou nd current of the ldo regulator. power dissipation due to the ground current is small and it can be ignored. t he total power dissipation in the adp5040 simplifies to : p d = {[ p dbuck + p dldo1 + p dldo2 ]} (13 )
data sheet adp5040 rev. 0 | page 33 of 40 j unction temperature in cases where the board temperature , t a , is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + (p d ja ) (14 ) the typical ja value for the 20 - lead, 4 mm 4 mm lfcsp is 38 c/w (see table 6 ). a very important factor to consider is that ja is based on a 4 - layer , 4 in ch 3 in ch , 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers . to remove heat from the device, it is i mportant to maximize the use of copper. copper exposed to air dissipates heat better than copper used in the inner layers. the exposed pad ( e p) should be connected to the ground plane with several vias as shown in figure 109. if the case temperature can be measured, the junction temperature is calculated by t j = t c + (p d jc ) (15 ) w here : t c is the case temperature. jc is the junction - to - case thermal resistance provided in table 6 . wh en designing an application for a particular ambient temperature range, calculate the expected adp5040 power dissipation (p d ) due to the losses of all channels by u sing equation 8 to equation 13. from this pow er calculation, the junction temperature, t j , can be estimated using equation 14. the reliable operation of the buck regulator and the ldo regulator can be achieved only if the estimated die junction temperature of the adp5040 (equation 14 ) is less than 125c. reliability and mean time between failures (mtbf) is highly affected by increasing the junction temperature. additional information about product reliability can be found in the analog devices, inc., reliability handbook , which is available at http:// www.analog.com/reliability_handbook . application diagram o n o f f f pw m pw m/ psm r filt 30? sw pg n d mo d e c4 10f l 1 1h vi n 1 en 3 en 1 vi n 2 vi n 3 en 2 a g n d vo u t 2 vo u t 1 fb3 vout3 c 1 4 . 7 f c 2 1 f c 3 1 f en _ b k buc k en _ l d o 1 l d o 1 (d igi t a l ) en _ l d o 2 l d o 2 (ana l og ) o n o f f o n o f f 4 1 6 1 3 1 0 7 6 3 ep 1 1 4 fb2 fb1 1 5 1 7 9 1 1 8 12 r2 r1 2 r7 r8 c6 2.2f r4 r3 v out1 at 1.2a c5 2.2f v in1 = 2 . 3 v t o 5 . 5 v v in2 = 1 . 7 v t o 5 . 5 v v in3 = 1 . 7 v t o 5 . 5 v v out2 at 300ma v out3 at 300ma 09665-103 avin figure 108 . application diagram
adp5040 dat a sheet rev. 0 | page 34 of 40 pcb layout guideline s poor layout can affect adp5040 performance, causing electro - magnetic in terference (emi) and electromag netic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following guidelines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high swi tching frequencies , and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? u se a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. suggested layout see figure 109 for an example layout. g p l n c n c n c a g n d n c 2 g p l g p l g p l g p l v o u t 3 v o u t 1 v o u t 2 p p l p p l p p l p i n 1 g p l g p l g p l g p l g p l g p l p p l p p l top layer 09665-102 vias legend: ppl = power plane (+4v) gpl = ground plane 2nd layer m o d e e n l1 ? 1h 0603 c5 ? 4.7f 10 v/xr5 0603 c6 ? 10 f 6.3v/xr 5 0603 1.0 1.0 2.0 2.0 3.0 3.0 mm mm 4.0 4.0 5.0 5.0 6.0 6.0 6.5 6.5 7.0 0.5 0.5 1.5 1.5 2.5 2.5 3.5 3.5 4.5 4.5 5.5 5.5 r filt 30? 0402 c3 ? 1f 10v/xr5 0402 c4? 2.2f 6.3v/xr5 0402 en3 vin 3 vout 3 fb 3 vout 1 fb 1 vin 2 vout 2 fb 2 c2 ? 1f 10 v/xr5 0402 c5 ? 2.2f 6.3v/xr5 0402 avin vin sw pgnd en 1 adp5040 figure 109 . evaluation board layout
data sheet adp5040 rev. 0 | page 35 of 40 bill of material s table 13. reference value part number vendor package c1 4.7 f, x5r, 6.3 v jmk107bj475 taiyo - yuden 0603 c2, c3 1 f, x5r, 6.3 v lmk105bj105mv -f taiyo - yuden 0402 c4 10 f, x5r, 6. 3 v jmk107bj106ma - t taiyo - yuden 0603 c5, c6 2.2 f, x5r, 6.3 v jmk105bj225mv -f taiyo - yuden 0402 l1 1 h, 85 m , 1400 ma lqm2mpn1r0ng0b murata 2.0 1.6 0.9 (mm) 1 h, 85 m , 1350 ma mdt2520 - cn t oko 2.5 2.0 1.2 (mm) 1 h, 89 m, 1800 ma xpl2010 - 1102ml coilcraft 1.9 2.0 1.0 (mm) ic1 3- regulator micro pmu adp5040 analog devices 20- lead lfcsp
adp5040 data sheet rev. 0 | page 36 of 40 factory programmable options table 14 . regulator output discharge resistor optio ns selection 0 all discharge resistors d isabled 1 all discharge resistors e nabled table 15. under voltage lockout options selection min typ max unit 0 1.95 2.15 2.275 v 1 3.10 3.65 3.90 v
data sheet adp5040 rev. 0 | page 37 of 40 outline d imensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compli ant t o jedec standards mo-220-wggd. 061609- b b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplan arity 0.08 pin 1 indica t or 2.65 2.50 sq 2.35 for proper connec tion of the expose d pad, refer to the pin configuration and function descri ption s secti on of this data sheet. 1 2 0 6 1 0 1 1 1 5 1 6 5 figure 110 . 20 - lead lead frame chip scale package [lfcsp_ w q] 4 mm 4 mm body, very very thin quad (cp - 20 - 10 ) dimensions shown in millimeters ordering guide model 1 uvlo active pull - down temperature range package description package option adp5040 acpz - 1-r7 2.15 v enabled on all channels t j = ?40c to +125c 20- lead lfcsp_wq cp -20-10 adp5040 cp -1- evalz evaluation board 1 z = rohs compliant part.
adp5040 data sheet rev. 0 | page 38 of 40 notes
data sheet adp5040 rev. 0 | page 39 of 40 notes
adp5040 data sheet rev. 0 | page 40 of 40 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d096665 - 0- 12/11(0)

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